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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>CMN (extended register) -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CMN (extended register)</h2>
      <p class="aml">Compare Negative (extended register) adds a register value and a sign or zero-extended register value, followed by an optional left shift amount. The argument that is extended from the &lt;Rm&gt; register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result, and discards the result.</p>
    <p>
        This is an alias of
        <a href="adds_addsub_ext.html">ADDS (extended register)</a>.
        This means:
      </p><ul><li>
          The encodings in this description are named to match the encodings of
          <a href="adds_addsub_ext.html">ADDS (extended register)</a>.
        </li><li>The description of <a href="adds_addsub_ext.html">ADDS (extended register)</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul>
    <p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">sf</td><td class="lr">0</td><td class="lr">1</td><td class="l">0</td><td>1</td><td>0</td><td>1</td><td class="r">1</td><td class="l">0</td><td class="r">0</td><td class="lr">1</td><td colspan="5" class="lr">Rm</td><td colspan="3" class="lr">option</td><td colspan="3" class="lr">imm3</td><td colspan="5" class="lr">Rn</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td></tr><tr class="secondrow"><td/><td class="droppedname">op</td><td class="droppedname">S</td><td colspan="5"/><td colspan="2"/><td/><td colspan="5"/><td colspan="3"/><td colspan="3"/><td colspan="5"/><td colspan="5" class="droppedname">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (sf == 0)</span></h4><a id="CMN_ADDS_32S_addsub_ext"/><p class="asm-code">CMN  <a href="#sa_wn_wsp" title="First 32-bit source general-purpose register or WSP (field &quot;Rn&quot;)">&lt;Wn|WSP&gt;</a>, <a href="#sa_wm" title="Second 32-bit general-purpose source register (field &quot;Rm&quot;)">&lt;Wm&gt;</a>{, <a href="#sa_extend" title="Extension applied to second source operand (field &quot;option&quot;) [LSL,SXTB,SXTH,SXTW,SXTX,UXTB,UXTH,UXTW,UXTX]">&lt;extend&gt;</a> {#<a href="#sa_amount" title="Left shift amount applied after extension [0-4], default 0 (field &quot;imm3&quot;)">&lt;amount&gt;</a>}}</p><p class="equivto">
      is equivalent to
    </p>
          <p class="asm-code"><a href="adds_addsub_ext.html#ADDS_32S_addsub_ext">ADDS</a> WZR, <a href="#sa_wn_wsp" title="First 32-bit source general-purpose register or WSP (field &quot;Rn&quot;)">&lt;Wn|WSP&gt;</a>, <a href="#sa_wm" title="Second 32-bit general-purpose source register (field &quot;Rm&quot;)">&lt;Wm&gt;</a>{, <a href="#sa_extend" title="Extension applied to second source operand (field &quot;option&quot;) [LSL,SXTB,SXTH,SXTW,SXTX,UXTB,UXTH,UXTW,UXTX]">&lt;extend&gt;</a> {#<a href="#sa_amount" title="Left shift amount applied after extension [0-4], default 0 (field &quot;imm3&quot;)">&lt;amount&gt;</a>}}</p>
          <p class="equivto">
          and is always the preferred disassembly.
        </p>
        </div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (sf == 1)</span></h4><a id="CMN_ADDS_64S_addsub_ext"/><p class="asm-code">CMN  <a href="#sa_xn_sp" title="First 64-bit source general-purpose register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>, <a href="#sa_r" title="Width specifier (field &quot;option&quot;) [W,X]">&lt;R&gt;</a><a href="#sa_m" title="Second general-purpose source register number [0-30] or ZR (31) (field &quot;Rm&quot;)">&lt;m&gt;</a>{, <a href="#sa_extend_1" title="Extension applied to second source operand (field &quot;option&quot;) [LSL,SXTB,SXTH,SXTW,SXTX,UXTB,UXTH,UXTW,UXTX]">&lt;extend&gt;</a> {#<a href="#sa_amount" title="Left shift amount applied after extension [0-4], default 0 (field &quot;imm3&quot;)">&lt;amount&gt;</a>}}</p><p class="equivto">
      is equivalent to
    </p>
          <p class="asm-code"><a href="adds_addsub_ext.html#ADDS_64S_addsub_ext">ADDS</a> XZR, <a href="#sa_xn_sp" title="First 64-bit source general-purpose register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>, <a href="#sa_r" title="Width specifier (field &quot;option&quot;) [W,X]">&lt;R&gt;</a><a href="#sa_m" title="Second general-purpose source register number [0-30] or ZR (31) (field &quot;Rm&quot;)">&lt;m&gt;</a>{, <a href="#sa_extend_1" title="Extension applied to second source operand (field &quot;option&quot;) [LSL,SXTB,SXTH,SXTW,SXTX,UXTB,UXTH,UXTW,UXTX]">&lt;extend&gt;</a> {#<a href="#sa_amount" title="Left shift amount applied after extension [0-4], default 0 (field &quot;imm3&quot;)">&lt;amount&gt;</a>}}</p>
          <p class="equivto">
          and is always the preferred disassembly.
        </p>
        </div>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Wn|WSP&gt;</td><td><a id="sa_wn_wsp"/>
        
          <p class="aml">Is the 32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Wm&gt;</td><td><a id="sa_wm"/>
        
          <p class="aml">Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xn|SP&gt;</td><td><a id="sa_xn_sp"/>
        
          <p class="aml">Is the 64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;R&gt;</td><td><a id="sa_r"/>
        <p>Is a width specifier, 
      encoded in
      <q>option</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">option</th>
                <th class="symbol">&lt;R&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">00x</td>
                <td class="symbol">W</td>
              </tr>
              <tr>
                <td class="bitfield">010</td>
                <td class="symbol">W</td>
              </tr>
              <tr>
                <td class="bitfield">x11</td>
                <td class="symbol">X</td>
              </tr>
              <tr>
                <td class="bitfield">10x</td>
                <td class="symbol">W</td>
              </tr>
              <tr>
                <td class="bitfield">110</td>
                <td class="symbol">W</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;m&gt;</td><td><a id="sa_m"/>
        
          <p class="aml">Is the number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;extend&gt;</td><td><a id="sa_extend"/>
        <p>For the 32-bit variant: is the extension to be applied to the second source operand, 
      encoded in
      <q>option</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">option</th>
                <th class="symbol">&lt;extend&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">000</td>
                <td class="symbol">UXTB</td>
              </tr>
              <tr>
                <td class="bitfield">001</td>
                <td class="symbol">UXTH</td>
              </tr>
              <tr>
                <td class="bitfield">010</td>
                <td class="symbol">LSL|UXTW</td>
              </tr>
              <tr>
                <td class="bitfield">011</td>
                <td class="symbol">UXTX</td>
              </tr>
              <tr>
                <td class="bitfield">100</td>
                <td class="symbol">SXTB</td>
              </tr>
              <tr>
                <td class="bitfield">101</td>
                <td class="symbol">SXTH</td>
              </tr>
              <tr>
                <td class="bitfield">110</td>
                <td class="symbol">SXTW</td>
              </tr>
              <tr>
                <td class="bitfield">111</td>
                <td class="symbol">SXTX</td>
              </tr>
            </tbody>
          
        </table>
        If "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases &lt;extend&gt; is required and must be UXTW when "option" is '010'.
      </td></tr><tr><td/><td><a id="sa_extend_1"/>
        <p>For the 64-bit variant: is the extension to be applied to the second source operand, 
      encoded in
      <q>option</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">option</th>
                <th class="symbol">&lt;extend&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">000</td>
                <td class="symbol">UXTB</td>
              </tr>
              <tr>
                <td class="bitfield">001</td>
                <td class="symbol">UXTH</td>
              </tr>
              <tr>
                <td class="bitfield">010</td>
                <td class="symbol">UXTW</td>
              </tr>
              <tr>
                <td class="bitfield">011</td>
                <td class="symbol">LSL|UXTX</td>
              </tr>
              <tr>
                <td class="bitfield">100</td>
                <td class="symbol">SXTB</td>
              </tr>
              <tr>
                <td class="bitfield">101</td>
                <td class="symbol">SXTH</td>
              </tr>
              <tr>
                <td class="bitfield">110</td>
                <td class="symbol">SXTW</td>
              </tr>
              <tr>
                <td class="bitfield">111</td>
                <td class="symbol">SXTX</td>
              </tr>
            </tbody>
          
        </table>
        If "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases &lt;extend&gt; is required and must be UXTX when "option" is '011'.
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;amount&gt;</td><td><a id="sa_amount"/>
        
          <p class="aml">Is the left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when &lt;extend&gt; is absent, is required when &lt;extend&gt; is LSL, and is optional when &lt;extend&gt; is present but not LSL.</p>
        
      </td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="adds_addsub_ext.html">ADDS (extended register)</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3>
    <p class="aml">If PSTATE.DIT is 1:</p>
    <ul>
      <li>The execution time of this instruction is independent of:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li>
      <li>The response of this instruction to asynchronous exceptions does not vary based on:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li>
    </ul>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
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